Nature

Phase-Locked Loop Design in CMOS Technology

Phase-locked loops (PLLs) are indispensable timing and frequency synthesis circuits, finding application in communication transceivers, clock distribution, navigation receivers and sensor interfaces.
EDN

Low Power Phase-Locked Loop with VCO

The 74HC/HCT4046A are phase-locked loop (PLL) with linear voltage-controlled oscillator (VCO) CMOS device having pins suited to 4046 in a 4000B series. These devices comply to JEDEC standard no. 7A.
Nature

Optical Phase-Locked Loop Technologies in Communication Systems

Optical phase-locked loops (OPLLs) are closed-loop control systems that stabilise and synchronise the phase of a slave laser with respect to a reference source, enabling coherent optical generation ...
EDN

Good behavioral model simulation: key to predicting first-order PLL synthesizer performance (Part 1 of 2)

In this article, the phase noise of a closed-loop, phase-locked loop (PLL) synthesizer is simulated using Agilent RF Design Environment (RFDE) and Advanced Design System (ADS) tools. The critical ...
Electronic Design

Measure Phase-Locked Loops With A Spectrum Analyzer

A general-purpose vector signal analyzer offers a low-cost, flexible option for measuring the frequency settling time of PLLs. By Douglas Olney, Keithley Instruments Inc. The frequency-settling time ...
Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 3)

A special technique produces very wide loop BWs in high-frequency PLLs (and hence, indirect (PLL) synthesizers), thereby achieving very low phase noise rivaling that of direct (MMD) synthesizers. A ...
EurekAlert!

Figure 2. Die micrograph of the proposed digital phase locked loop (PLL) (IMAGE)

The total power consumption of the proposed PLL is only 8.89 mW from a 1 V supply, which leads to a figure of merit of reference of -247.4 dB. Credit must be given to the creator. Only noncommercial ...